Analysis of MOS Memory Circuits - Term Paper Example

MOS MEMORY CIRCUITS   By (Student’s Name)   Course Title Instructor’s Name University Location Date Table of Contents Table of Contents 2 MOS Memory Circuits 3 Introduction 3 Volatile Memories 3 Dynamic Random Access Memory (DRAM) 4 Performance of DRAM 5 Static Random Access Memory (SRAM) 9 Operation of SRAM 11 Standby 12 Reading 13 Writing 13 Bus behaviour 13 Non-Volatile Memories 14 EEPROM (Electrically Erasable Programmable Read-Only Memory) 14 FLASH 15 Amplifiers 16 Class AB Amplifiers 16 Bipolar 17 MOSFET 18 Comparison between BIPOLAR and MOSFET 18 References 20 MOS Memory Circuits Introduction MOS memory circuits have become very popular in the recent past as rapid development is witnessed in the field of Information Communication and Technology. They are particularly applied in electronic devices for instance such as computers, radios, digital cameras and Television sets among others. However, their use in the aforementioned devices varies depending on the purpose of application. Reason being MOS memory circuits are categorised either as volatile or non-volatile. This classification is based on the capacity for either of the two to maintain and preserve information contained in them in case of power surge and of power blackout (Sze, 2001). In comparing between the two, information contained in volatile memories is lost as contrasted to non-volatile memories whereby information/data is preserved (Integrated Circuit Engineering Corporation, 1997). In this regard, the first section of this research essay takes a closer look and discusses various kinds of memory circuits that include a. Volatile memories –NMOS static RAM, CMOS static RAM and Dynamic RAM b. Non-Volatile Memories –ROM, PROM and EPROM. In the second section, class AB amplifiers are described in respect to their output stages for both Bipolar and MOS transistor circuits. Volatile Memories As earlier mentioned, volatile memories do not have the capacity to retain information/data and they therefore require to be supplied with power so as to maintain storage of such information/data. Majorly there are two types of volatile memories as discussed below. Dynamic Random Access Memory (DRAM) DRAM is a kind of RAM with capacity to store every bit of information/data in an isolated capacitor inside the integrated circuit. DRAM consists of a storage capacitor and single MOS transistor as illustrated in the figure below. Figure 1. DRAM Cell Based on the fact that capacitors may leak charge, information/data in it is gradually lost unless, periodically, the charge of the capacitor is refreshed. Due to the process of refreshment, it is referred to as dynamic memory in contrast to Static Random Access Memory and other static memories. Nevertheless, DRAM has a lot of benefits due to its simplicity in terms of structure. First, it requires a single capacitor and a transistor for every bit as compared to the six transistors required in SRAM. As such, it this enables DRAM to attain a very high density. Secondly, as opposed to flash memory, DRAM is volatile in that data is lost when power supply is cut off. Third, the capacitors and transistors used are exceptionally small and several million pieces can be put together in one memory chip (Integrated Circuit Engineering Corporation, 1997). Performance of DRAM In terms of arrangement, DRAM has a single transistor and a capacitor per cell put in a square array. This is illustrated in the figure below. Figure 2. DRAM Performance In the above figure, the cells are arranged in a 4x4 array and the each row is connected by long lines that are referred to as word lines. In every column, there is a pair of bit lines with each one of them being connected to each storage cell within the column. They are usually referred to as positive and negative bit lines. In the case of a sense amplifier, there are usually two cross-connected inverters in between the bit lines. This mean that the first inverter is usually linked from the positive bit line to the negative bit line whereas the second inverter is linked form the negative bit line to the positive bit line. Such is an illustration of a positive feedback but the arrangement is stable only with a single bit-line high as well as a single bit-line low. Several operations take place when reading a bit from the column and they include; first the sense amplifier is powered off bit lines are pre-charged to attain the same voltage which is intermediate between low and high logic levels. Besides, bit lines are symmetrically constructed so as to stabilize them as exactly as possible. Second power supply to the pre-charged circuit is cut off and due to the lengthy bit lines; their capacitance is capable of holding the pre-charge voltage for a short while. This is a true illustration of dynamic logic. In the third stage, the chosen rows are driven high in order to link a storage capacitor to any of the bit lines. Due to this, the suitable bit line and the selected storage cell shares the charge thereby altering the line’s voltage to some extent. Although there are some efforts made so as to maintain the capacitance so as to highly maintain storage cells’ capacitance as well as the low capacitance of bit lines, the capacitance is comparative to physical size, and the size of the bit lines means that the net result is a small perturbation of voltage of the bit lines. Subsequently, the sense supplier is powered on rendering positive feedback to be initiated and amplify the relatively small voltage difference up to the when one bit line becomes totally low whereas the other one it totally full. At this instance, the row becomes open and selection of a column can be done. In addition, read data contained in DRAM is extracted from sense amplifiers after selection by column address. As such, several reads can be executed while the row is still open in that manner. Whereas reads continues to proceed, current flows back upwards on the bit lines right to the storage cells from the sense amplifiers. In that case, charge within the storage cell is refreshed. Because of the bit lines’ length, the process takes quite some time until the sense amplification comes to an end whilst overlapping of at least one column reads. Upon completion of the current, storage capacitors are disconnected by switching off the word line, sense amplifies is powered off whereas the bit lines are once recharged. Figure 3. DRAM Data selection process In order to write memory, row is opened whereas column sense amplifier is provisionally forced to attain the value required state in order to drive the bit line that charges the capacitor to the recommended value. As a result of the positive feedback, the amplifier is capable of stabilizing after the removal of the forcing. During the writing process to a specific cell, the whole row is read out and the value is adjusted, and the whole row is inscribed back in as described in the above diagram on the right section (Howstuffworks.com, 2012). Static Random Access Memory (SRAM) SRAM is type of semiconductor memory in which case the word static means that as opposed to DRAM it does not require period refreshment (Electronics Engineering Herald, 2006). Reason, being SRAM makes use of bi-stable latching circuitry in order to store every bit. On the other hand, SRAM displays data remanence although conventionally it is still volatile in that when power goes off, data is lost. As illustrated in the figures 2a below, SRAM comprises of a bi-stable flip-flop that is connected to an internal circuitry by a pair of transistors. Figure 4. SRAM cell Every bit contained in an SRAM is amassed on four numbers of transistors, which shape the two numbers of cross-coupled inverters. The storage cell is consists of two states of equilibrium that are employed to represent 1 and 0. The two added access transistors aid in controlling entrance into a storage cell while write and read operations are taking place. To store every bit of memory, an archetypal SRAM employs six MOSFETs. Besides 6T SRAM, there are other SRAM chips which employs 10T, 8T, or extra transistors in every bit, an aspect that is sometimes employed in implementing over one write and/or read port, that can be valuable in particular types of register files and video memory implemented with multiple circuitry ported SRAM (Ibid, 2006). Generally, the size of the cell is determined by the number of transistors that a cell can hold; the fewer the number of transistors the smaller the cell. Due to the fact that the silicon wafer processing cost is comparatively fixed, employing smaller cells and therefore, packing extra bits on a single wafer lowers the cost in every memory bit. It is possible to have a memory cells that uses less than 6 transistors although, they should not be very low; Cells such as 1T or 3T are not SRAM cells but DRAM cells. Word line (WL) is a command used to enable access into the cell. The command controls the two M6 and M5 access transistors, which consequently determines the bit lines that the cell should be connected to. These bit lines are used in data transfer for both operations of write and read. Although, the two bit lines are not very necessary, both the signal as well as its inverse is characteristically provided so as to improve the margins of noise (Paris, 1998). The SRAM cell inverters actively drive the bit lines low and high throughout read accesses. This improves the bandwidth of SRAM as compared to that of DRAMs where the bit line is linked to storage capacitor where it swings downwards or upwards due to charge sharing. Additionally, the SRAMs symmetric structure allows for degree of difference in signalling that easy the detection of minute voltage swings. Another aspect that creates a difference between SRAM and DRAM is the capability of SRAM commercial chips to accept every address bits each at a time, a feature that makes SRAM faster than DRAM. On the other hand, the address of commodity DRAMs is multiplexed into two equal parts; the lower bits following the upper bits, over the identical pins’ package so as to maintain their low cost and small size. The SRAM’s size is determined by the product of number of data lines (n) and two raised to the power address lines number(m); n x 2m (Patsnap.Com, 2012). Operation of SRAM There are three dissimilar states in which SRAM cell can be operate in. These states include a standby state where the circuit is inactive, reading state when requesting of data takes place and writing states when the contents is being updated. For a SRAM to function in write and read mode it should contain writing stability and reading ability respectively. In particular, the read/write operations are diagrammatically illustrated in figures 3a and 3b below and subsequently discussed. Figure 5a Read/Write Operation Figure 5b. Read/Write operation Standby The cell is disconnected from the bit lines by M6 and M5 access transistors if the assertion of the word line did not take place. Provided that the two numbers of cross coupled inverters created by M1 to M4 are linked to the power supply, they will keep on reinforcing each other. Reading With an assumption that the memory content is 1, and Q is the storage point, the read cycle is initiated by pre-charging the two bit lines to a level logical 1, followed by word line WL asserting, enabling the two access transistors. The second step happens when Q and the value stored in it are moved to the bit lines by leaving BLi to replace its pre-charged value and discharging to a logical 0 BLo from M1 through to M5. On the side of BLi, bit-line is pulled in the direction of VDD by the transistors M6 and M4, to a logical 1. If the memory content were a 0, the reverse could happen where BLi would be dragged toward 1 and BLo in the direction of 0. Writing The write cycle starts by applying to the bit-lines the bit to be written. If 0 is the bit to be written, then 0 is applied to the bit-lines; setting BLi to 0 and BLo to 1. This is the same as applying a reset pulsates to a SR-latch that causes the change of status in the flip flop. To write on A1 the bit-lines values should be inverted then, the word line is asserted and the bit to be stored is latched in. It should be noted that this process works because the input–drivers of the bit-lines are intended to be more stronger than the transistors located inside the cells which are relatively weak, so as to easy their overriding the past cross-coupled inventers state. At this level, careful transistors sizing in an SRAM cell is required to make certain proper operation (Gaurav, 2010). Bus behaviour Memory of a RAM with 70ns access time will give valid data output within 70ns as long as the time address lines are applicable. Other than that, the data will be on hold for a period of time. In addition, fall and rise times powers suitable timeslots with roughly 5 ns. By analysing the lower address part range bits in cycle, one can read with considerably shorter right of admission time. Non-Volatile Memories Non-volatile memory is computer memory which keeps stored information even when power goes off. Non-volatile memory examples include flash memory, read-only memory, computer magnetic storage devices such as magnetic tape, floppy disk, hard disk, optical discs, and old computer methods of storage such as punch cards and paper tape. Non- volatile memory is commonly used for secondary storage tasks for long-term constant storage. Currently, the form of primary storage that is widely used is random access memory (RAM) which is a form of volatile memory, implying that once a computer is switched off any data contained in RAM will be lost. It is unfortunate that almost all forms of non-volatile memory contain limitations which make them inappropriate to be employed as primary storage. The most commonly form of non-volatile memory used today include FLASH and EEPROM memory (Integrated Circuit Engineering Corporation, 1997). EEPROM (Electrically Erasable Programmable Read-Only Memory) EEPROM is a form of Read Only Memory that can be modified by users through erasing and rewriting or reprogramming repeatedly by application of electrical voltage that is above the normal value. This is illustrated in he Contrary to EPROM chips, while programming EEPROM, removing the chip from the computer is not necessary. However, it is not possible to program the chip selectively; the chip has to be programmed entirely. Another limitation is EEPROM’s life is limited; it has a limitation on the number of time it can be reprograms either in thousands, hundreds or tens. In a situation where EEPROM is regularly reprogrammed when the computer is still operating, EEPROM life can be an essential consideration in design (Integrated Circuit Engineering Corporation, 1997). Figure 6. EPROM/Flash cell FLASH Flash memory is a permanent computer storage that can be reprogrammed and erased electrically. Flash memory is a technology which is chiefly employed in USB flash drives and memory cards for general storage and data transfer between different digital products as well as computers. It is a specific form of EEPROM that is programmable and erasable in large blocks; in old flash, reprogramming erase entire content at once. Flash memory is far much cheaper as compared to byte programmable EEPROM therefore, it has been the most widely used technology in situations where an important amount of permanent or non-volatile storage is needed. Some of places where flash memory is applied include mobile phones, digital cameras, digital audio players, laptop computers, personal digital assistants (PDAs). Additionally, flash memory has increased its popularity in the hardware of console video game, where it is frequently used in place of battery- powered static RAM (SRAM) or EEPROMs to save data of the game (Ibid, 1997). Flash memory is permanent and therefore no power is required to hold the information stored in its chip. Additionally, flash memory gives fast times to read access and improved resistance to kinetic shock as compared to hard disks. These features explain flash memory popularity in portable devices. Another flash memory characteristic is that it is very durable once wrapped up in a memory card it is capable of enduring temperatures extremity, intense pressure, as well as immersion in water. A trawler man tried to trace digital camera’s owner after being dragged from seabed of Atlantic in his fishing nets with photos still in place. Although flash memory is a technical form of EEPROM, EEPROM is a term generally employed to specifically refer to non-flash EEPROM that is erasable in minute blocks, characteristically bytes. Since erase cycles work at low speed, the large sizes of blocks employed in flash memory deleting offer it a significant advantage of speed over old technology EEPROM when writing data in large quantities. There are two existing flash memory technologies which include NAND and NOR flash. Their main differences include different individual memory cells connections and different writing and reading memory interface; NOR permits reading random access while NAND permits page access only (Ibid, 1997). Amplifiers Class AB Amplifiers Class A amplifiers make use of a similar transistor so as to generate both the bottom and top halves of a signal. In that case, the output transistor is more oriented to an inactive conduct and current for the whole cycle of the input signal. However, are only 25% efficient and hence they are not better in terms of performance. In the case of class B amplifiers, an output transistor conducts for a half of every sine in the wave cycle. In some cases, it makes use of a pair of transistors so s to produce a full signal; one transistor generates the top half whereas the other half generates the bottom half of the signal. One advantage is that they are 78.5% efficient and hence better in terms of performance. Subsequently, for class AB amplifiers, the output transistor is more oriented to an inactive conducts and current which is slightly higher than a half cycle. They make use of a pair of transistors similar to that used in class A and the quality of signal is better-off compared to that of class B. besides, they have no crossover distortion as compared to class B and they are therefore employed in audio amplifiers (Perry, 2012). Bipolar As earlier mentioned, it is possible to reduce crossover distortion by applying a small inactive bias on every output transistor. Theoretically, VBB /2 is employed at the base of the emitter junction, Qn, and as well similar level of voltage, VBB /2, is employed to the emitter at the base junction, Qp. Therefore, vi = vo = 0 which means that that the inactive collectors within in both transistors are equivalent i.e. iCn = iCp = Is*e^ VBB /2. In that case, a small increase of vi results in a proportional increase of vo at the base of Qn and this acts as a subsequent emitter for distributing current to RL . Hence, the output is calculated as Vo = vi + VBB /2 –vBEn Subsequently, iCn is the collector of current Qn which is given as, iCn= iL + iCp. In the same regard, even in the case of a zero-output signal, inactive collector current occurs within the output transistor. Therefore, the power utilized in the two transistors is larger as compared to class B rendering it to be less efficient. However, it has more capacity to handle large power volumes that class B (Donald, 2009). MOSFET In the case of MOSFET transistors, they are connected to each of them in such a way that Mn and Mp are matched. On the other hand, vi=0 whereas VBB/2 is employed at the gate source Mn and similar voltage of VBB/2 is employed at source gate Mp. In that case, the drain current is every transistor is calculated as iDn = iDp = IDQ= k (VBB /2 - |Vt|) ^2. An increase in vi results in an increase in the voltage of gate Mn and subsequent increase in vo and as well the same transistor gives load current to RL. On the other hand, an increase in iDn results in proportional increase of VGSn and in cases where there no voltage change of VBB, then a decrease in VGSp results (this as well decreases current flowing through iDp and Mp). An increase in negative value of vi results in an increase in voltage vo in which case transistor Mp as a basis follower drawing current for the load (Donald, 2009). Comparison between BIPOLAR and MOSFET Both BIPOLAR and MOSEFT have a lot of advantages and disadvantages especially in industries manufacturing audio devices. In the case of bipolar transistors, they have the capacity to supply high current rates into several loads which is favorable for low frequencies. In the case of MOSFET, they are known for providing best output results in cases of mid- and high- frequencies (Kuells, 2001). Usually, a MOSFET transistor functions as a water valve in that upon application of voltage to the gate, the current flows form its points of supply to the drain. In previous models of MOSFET, the drains that were employed resulted into high internal impedances thereby affecting sound quality instances of low frequencies. On the other hand, BIPOLAR is capable of delivering large amounts of current to the load thereby resulting into high rate of current flow form the base of the transistor to the emitter. In terms of design, BIPOLAR requires substantial drive stage and heat sinking based on the fact that every transistor’s base is driven by current and it emits huge loads of heat (Ibid, 2001). In the case of MOSFET, a drive stage is required although there is no much current load because they are heavily driven by voltage. On comparison basis, one of the problem with BIPOLAR is that they must be used along with emitter transistors so as to share the load in order to regulate the amount of heat and failure to which will blow up the device. In the case of MOSFET, its design is more stable and incase of heat increase, internal resistance increases as well thereby reducing the rate of power flow. Hence they have a less chances of experiencing thermal runaway. In case they fail, it is not highly possible to damage the speaker and they do not require a direct current circuitry. Conversely, in case a BIPOLAR fails it is highly possible for all the devices to incur a lot of damage due to power surge. Generally, MOSFET are more expensive, versatile and have the capacity to switch a number of lamps within a few seconds than BIPOLAR (Tomshardware, 2012) References Read More