Operating System - Virtual Memory with Paging - Literature review Example

Introduction Virtual Memory with paging and segmentation has been key aspects in the management of memory, especially if the memory will have to be shared among different users or multiple concurrent tasks. Modern CPUs have increased memories and some have adopted long address fields known to be generating large spaces needed. However, the amount of actually installed memory remains a limiting factor in most computers. This brings the aspect of virtual memory which is capable of addressing the problems of sharing the little memory through OS software mechanisms and architectural designs. This brings the aspect of virtual memory with paging and virtual memory with segmentation. This report intends to present a summary on virtual memory with paging and virtual memory highlighting key issues in each case. Virtual Memory with Paging Within this context, Tanenbaum, (2001) defines paging as the process whereby the address space is given a division into fixed-size pages. The author is an experienced programmer and this book elaborates latest developments and analysis in operating systems technologies incorporates new technologies in computer. This definition is well supported in his earlier works which defines paging as a process where physical memory is divided into sections or chunks known as page-frames. Each page-frame is 4KB on Pentium. On the other side, virtual memory is a feature that has the ability of simulating additional main memory such as random access memory. That is virtual memory should be an automatic address translation providing elements such as decoupling “name space” of a program from physical location. Paging, involves treating virtual address as a pair---that is (p,o). Whereby high-order bits is intended to give specification to page p and on the other hand, lower order bits offsets o within the a given page. Giving a practical example of the scenario above, assuming that there is 1KB in each page and 16 bits of virtual address. Then 10 bits which is the lower-order will give the offset whereas 6 bits which is high-order will give the system page number. He also explains the role of Memory Management Unit (MMU) which is closely related to paging process. Page number p is translated to a frame number f by the MMU. This gives physical address which is actually (f,o) which goes on the memory bus. Russinovich and Solomon (2005) bring an interesting point by arguing that for every process as explained above; there is an array, actually a page-table. This book primarily discusses advanced features of NTFS and the management of memory in a computer. And for translation, page number which is regarded as p functions as an index into this page table (array). This brings another important process; Page Table Entry. In the event that corresponding page is available in the memory then there is a need to set validity bit at 0. Other important issues he advices when making page table entry is that when estimating frame number, bits needed is depended on size of available physical memory. Also, when the page is used by the policy of page replacement (accessed) then referenced bit should be set at 1 by the hardware. There are some issues that engineers might encounter in the process of designing. For instance, the page desired cannot be found in the memory. This is an instance of a page fault which traps to kernel. It is important to point out that page daemon has the ability to run periodically so that there is enough free memory and thus a page is loaded from the disk as soon as there is page fault. However, there come situations where multi-level paging is ideal. During the proceedings of the international workshop on the memory management, the workshop detailed comprehensive steps that can be adopted when undertaking multi-level paging. Wilson and Johnstone (1995) explain that during the conference it was becoming cumbersome for instance, trying to keep a page-table with 230 entries in a single table. There need to be a page table made in hierarchical manner to offset that. For instance, latest Pentium have the ability of supporting two-level paging. He further argues that when dealing with inverted page tables an assessment to ascertain whether virtual memory is larger than the physical memory is needed. During the proceedings of the 25th international symposium on computer architecture, Swanson et al. (1998) argue that a situation arises where we have a 64-bit computer with 4KB per given page and 256 Megabytes memory. This symposium dealt mainly with thread level parallelism concerning the MIT Multi-ALU processor. In this particular case, the machine has 64K page-frames but 252 but we have overhead storing page-table being so high. Solution to this issue is that at any given point, the machine may require about 64K entries when the inverted page table stores entries of the process id or page frame. Supposing there is a page p with process y finding its corresponding page frame will be first, considering the use of hashing since linear search will be too slow. But at the same time a mechanism has to be adopted that will handle incidences such as hash-collisions. This is practiced by some HP and IBM workstations. Steps in Paging Steps needed in paging have been elaborated by Bovet and Cesati (2002). This book explains aspects from the point view of the symposiums earlier hosted. It further details on the information concerning rootkits, specifically for Linux. They explain that there need to be special hardware support to necessitate paging. However, it can be noted that modern systems can adopt Translation Lookside Buffers (TLBs) and multi-level paging. An overview procedure involves: Input to MMU: page p, offset 0 =virtual address Ensuring that TLB has a frame f with (p, f) In that event physical address is expected to be (f,0) If this is not the case page-table in main memory needs checking. There could be a couple of accesses resulting from multi-level paging) If there is page, the next step is to do computation of physical address Alternatively, processing page-fault can be done by trapping kernel Updating of page-table entries/TLB for example modified bit Page Fault Handling In the event there is a page fault, page fault handler will be an ideal tool. This will ensure that there is swapping of a page from the concerned disk into the memory. Other processes detailed in the research involve: Ensuring that registers of current process are saved Checking the availability of free frame, in case there is none, invoking page replacement policy to select one is recommended The process needs to write selected frame to disk if it is dirty. Otherwise, scheduling of I/O to do the reading in the page will be necessary if the frame is clean Ensuring that page table is up to date Rescheduling of the process causing fault Instruction behind fault reinstated (risk affair to engage in) Restoration of registers and programme should be able to execute Virtual Memory with Segmentation Windows have the ability of working a number of architectures. The fact that some windows have been designed to support both 64 bit and 32 bit logical addresses takes memory management to the next level. Such revolution includes OS creating multiple virtual address space. Every specific virtual space starts at arbitrary length and arbitrary location. This is preliminary information that guides virtual memory with segmentation. However, researches points at different issues involved when virtual memory with segmentation is brought in the picture. Starting with Guertin (1972), this book explains that the process of segmentation as it is closely related with that of paging, through what the author describes as a lookup table. However, it needs to be explained that unlike the process earlier analysed regarding paging, in segmentation, every segment descriptor within the table has the base address of the length and segment. With regard to its efficacy, segmentation solves the problem in a unique way. During his research, Multics and IBM System/38 has been cited as some examples where the efficiency of segmentation was experienced. It actually does the implementation of virtual memory as a collection address spaces each being a segment ranging in sizes. Arguing about what the IBM does exactly, it Bryant (1975) explains that the company allows their systems to mirror the organisation of specified application by the use of a different or separate segment for every logical component. Logical component may include a stack, a table or an array. Writing about Predicting workshop set sizes of IBM, this article also brings the aspect of logical names which can be translated by the loader or in some cases, linker into segment numbers. These are the numbers that will finally be able to one of the many segments. An offset within every segment will be tasked in the identification of a unique or specific word. This is where the similarity with page implementation with virtual memory comes in. An address (virtual) va using segmentation will as well consist of (s,w), w being the offset and s the number of the segment. For the purposes of clarification, segment numbers relates to logical components of the specified programme whereas page number as highlighted above has not correspondence with the structure of the programme. An article written by Smith, (1978) on bibliography on paging and related topics brings the element of schemes used for building a segmented virtual memory. The article further explains the two different schemes that can be used in the process of building a segmented virtual memory. While the first scheme can be able to treat the segment as the basic unit for the allocation of memory and make assumption that memory can be allocated dynamically and relocated in variable size blocks, the second scheme on the other hand uses paging as an alternative for allocating for the allocating space for a segment. This simply means that every segment can be sub-divided into pages with fix pages so as to facilitate allocation. In some cases, a situation arises where a segment may be given allocation but such goes unused. This is when segmentation suffers an internal fragmentation. This article further brings the concept of checkerboarding. With checkerboarding, a situation arises where the variable size of the segments is able to lead to external fragmentation. According to Bensoussen and Clingen (1999), external fragmentation further entails de-allocation and allocation of space for process that have segments of varied sizes leaving a collection of holes which are very small to accommodate new processes. Bensoussen and Clingen detail on MULTICS virtual memory-conceptsand design. To avert external fragmentation, compaction process is needed. Compaction works on the principle that all active processes can temporarily be suspended thereafter relocated so as to gather together every memory holes. Applying compaction to Intel machines for instance may be expensive because they already have large volumes of physical memory. Contiguous Allocation Per Segment As applied in page table, Love (2005) also explains that segment table can be used for every active process so that current segments are tracked. Basically, the is sequential numbering of segments with the ith (i=0,1,…) found in the segment table. This corresponds to segment number i. The system always treats the segment table as a segment. The starting point of any segment table (usually of the one running process) is maintained in a register referred to by the author as segment table register (STR). (s,w) a virtual address will therefore get mapped to a (pa) physical memory as indicated below: address_map(s, w) { in the event that ( resident(*(STR+s)) ) { pa = *(STR+s)+w; return pa; } else segment fault; } References Bensoussen, A.C., and Clingen R.C. (1999) “The MULTICS virtual memory-conceptsand design” Communications of the ACM, 15 (5), 308-318. Bovet, D.P., and Cesati (2002). Understanding the Linux Kernel, O’reilly,Sebastopol. Bryant, P. (1975). Predicting workshop set sizes. IBM Journal of R and D, 19 (5), 221-229 Guertin, R.L (1972). Programming in a paging environment. Datamation, 18 (2). 48-55. Smith, A.J (1978). Bibliography on paging and related topics. Operating Systems Review, 12 (4), 39-56. Love, R. (2005). Linux Kernel Development , Second edition, Novell Press. Russinovich, M.E. and Solomon D.A. (2005): Microsoft Windows Internals, Fourth edition, Microsoft Press, Redmond. Swanson, M.L., Stoller, J.N and Carter, G. (1998). Increasing TLB reach using super-pages backed by shadow memory, Proceedings of the 25th International Symposium on Computer Architecture, 204-213 Tanenbaum, A.S. (2001). Modern Operating System, 2nd edition, Prentice-Hill, Englewood Cliffs. Wilson, P.R., and Johnstone, M. (1995). Dynamic storage allocation: A survey and critical review, Proceedings of the International Workshop on the Memory Management, 1-116. Read More